This invention relates to clocked integrated circuits that deliver data, and more particularly to a method and apparatus for adjusting the timing of data presented to an output terminal relative to a clock signal.
Clock signals are used by a wide variety of digital circuits to control the timing of various events occurring during the operation of the digital circuits. For example, clock signals are used to designate when command signals, data signals, and other signals used in memory devices and other computer components are valid and can thus be used to control the operation of the memory device or computer system. For instance, a clock signal can be used to develop sequential column addresses when an SDRAM is operating in burst mode.
Retrieving valid data from a clocked memory device at a specified time can be difficult to coordinate. After a memory address is selected, the data travels out of the selected memory cell, is amplified, passes through configuration circuitry (if the memory chip has multiple configurations) and passes through an output buffer before the data is read. Before the advent of synchronous memory circuits, data simply appeared at an output terminal following a propagation delay after the data was requested. In a synchronous memory circuit, data delivery is synchronized with a clock signal. Many circuits have been created to coordinate data signals with clock signals, with varying degrees of success. Two of the problems to solve are determining how fast and with what regularity the data signal propagates through the chip circuitry. Because data output is often coordinated with a clock signal that is external to the memory chip, computer simulations of signal propagation within a chip are performed to align the external clock signal with the data delay of the synchronous memory device. Static time delays are then designed into the memory circuit based on the simulation predictions. Because of production variations, improper assumptions, and other factors ultimately causing timing errors, the data does not always arrive at the output terminal at the desired time. As computer clock speeds increase, the window for providing valid data to the output terminal closes, making it more difficult to ensure the correct delivery time of data from the memory circuit.
An example of a circuit that provides data to a data pad at a specific time relative to an external clock is shown in FIG. 1. An output circuit 2 includes a memory array 5 that contains an array of individual memory cells (not shown). Once a particular memory cell is selected to be read, complementary signals corresponding to the contents of the memory cell travel to a pair of respective I/O and I/O* lines. The signals on the I/O and I/O* lines are sensed and amplified by a data sensing circuit 10, which produces a DATA* signal at an output. An external clock signal is received at a clock circuit input 7 and passes through clock circuitry 15 to become a CLKDOR* signal. The CLKDOR* signal may differ from the external clock signal in a variety of ways, including phase, orientation, and duty cycle, however, their overall periodic cycle length is the same. Oftentimes, to properly match timing of the data arriving at the data pad with the external clock signal, a static delay is added within the clock circuitry 15.
The DATA* signal is presented to a passgate 20 and passed to an output node 21 when the signal CLKDOR* signal is HIGH and its complement from an inverter 17 is LOW. From the output node 21, the DATA* signal is input to a NOR gate 30 along with a TRISTATE signal. An output from the NOR gate 30 leads to a passgate 24. When the CLKDOR* signal is LOW and its complement from the inverter 17 is HIGH, the output from the NOR gate 30 passes through the passgate 24 and becomes the signal DQHI. Another NOR gate 32 combines the output of the NOR gate 30 with the TRISTATE signal. This output from the NOR gate 32 is presented to a pair of passgates 22, 26. The passgate 22 receives the signal from the NOR gate 32 and, when the CLKDOR* signal is LOW and its complement from the inverter 17 is HIGH, feeds it back to the output node 21. The passgate 26 passes the signal it receives from the NOR gate 32 as an output signal DQLO when the signal CLKDOR* is LOW and its complement from the inverter 17 is HIGH.
If the signal DQHI is HIGH, a pull-up circuit 36 raises a DQ pad 40 to a HIGH voltage. Conversely, if DQLO is HIGH, it activates a pull-down circuit 38 to pull the DQ pad 40 to a ground voltage. The output circuit 2 is designed so that the pull-up circuit 36 and the pull-down circuit 38 cannot operate simultaneously. When neither the pull-up circuit 36 nor the pull-down circuit 38 is active, the DQ pad 40 is neither pulled up to a HIGH voltage nor pulled down to ground, but instead remains in a high-impedance state.
The circuit operation of the data delivery circuit 2 will now be explained. When the CLKDOR* signal is HIGH and the DATA* signal is HIGH, a HIGH signal passes to the output node 21. Assuming that the TRISTATE signal is low to enable the NOR gates 30 and 32 so they act as inverters, when the CLKDOR* signal goes LOW, the passgate 22 couples the output of the NOR gate 32 to the input of the NOR gate 30, output node 21. The NOR gates 30 and 32 then latch the HIGH at the output node 21 to the output of the NOR gate 32. At the same time, a LOW is latched to the output of the NOR gate 30. The HIGH at the output of the NOR gate 32 is coupled through the passgate 26 to the pull-down circuit 38. The HIGH signal DQLO causes the pull-down circuit 38 to pull the DQ pad 40 to ground. At the same time, the LOW signal at the output of the NOR gate 30 passes through the passgate 24. The LOW DQHI signal does not activate the pull-up circuit 36, as explained above. Alternatively, if the DATA* signal is LOW, a LOW signal is passed to the output node 21 when the CLKDOR* signal is HIGH. When the CLKDOR* signal drops LOW, the LOW signal at the output node 21 is latched by the NOR gates 30 and 32, is fed back to the output node 21 through the passgate 22, and also propagates through the passgate 26 to make DQLO LOW. Concurrently, the LOW signal at the data output node 21 causes the NOR gate 30 to output a HIGH signal that passes through the passgate 24 to provide a HIGH DQHI signal. The HIGH DQHI signal causes the pull-up circuit 36 to connect the DQ pad 40 to a HIGH voltage. If the TRISTATE signal is HIGH, neither DQHI nor DQLO will be HIGH regardless of the state of the DATA* signal. Thus, the DQ pad 40 floats in a high impedance state.
When a computer system is designed, specifications for signal timing are determined. Some of the signals and timings used in the design are shown in FIG. 2. One of the design specifications is an access time, TAC, used to designate a maximum time between a rising edge of an external clock signal and when a valid data signal arrives at the DQ pad 40. Additionally, another specified time parameter is the output hold time, TOH, indicative of a minimum time for how long the data will be held at the DQ pad 40 following a subsequent rising edge of the external clock. For example, as illustrated in FIG. 2, a READ command signal is input to a memory circuit sometime between a rising edge of a clock pulse CP0 and a clock pulse CP1. At a time CP1, the READ command is latched and read by the memory circuit, indicating data is to be read from a memory cell in a memory array. The data is read from the array and placed at the DQ pad 40 under the control of the CLKDOR* signal. The specification TAC indicates a maximum time until the desired data is placed on the DQ pad 40. The data is held at the DQ pad 40 for a time no less than the specification TOH, as measured from a subsequent clock pulse after the READ command is latched. As shown in FIG. 2, TAC1 is the time measured from CP2 until Data1 is stable on the DQ line. TAC2 is the time measured from CP3 until Data2 is stable on the DQ line, and so on. The time TAC1 will be nearly identical to the other access times TAC2, TAC3, etc. under the same operating conditions. Also shown in FIG. 2, TOH1 is the time measured from the next clock pulse following when Data1 appears on the DQ line, i.e., CP3, to the time when Data1 begins to transition off the DQ line. As above, the measured hold times TOH2, TOH3, etc. will be nearly identical to one another under similar operating conditions.
During the design phase of a memory chip, a designer determines how much after each clock pulse the CLKDOR* signal should fire. This delay determines when the data is made available on the DQ line relative to the external clock signal. Typically, a delay value is chosen that provides a tolerance for both the TAC and TOH parameters. If the CLKDOR* signal fires too soon after the external clock signal, the chip will easily pass the TAC specification, but may fail the TOH specification. If the CLKDOR* signal fires too late, the chip will easily pass the TOH specification but may fail the TAC specification. These time compensations, by virtue of being fabricated as part of the circuit, generally cannot be changed after manufacture of an integrated circuit. When memory chips fail their timing specifications, they are sold as lesser quality chips for a reduced price, or even destroyed. Thus, there is an economic incentive to maximize the number of chips that meet or exceed the timing specifications. As a consequence of increasing computer speeds, this already small window for proper data timing is reducing. Because of process variations, errors in design assumptions, the wide range of temperatures and voltages in which the chips are warrantied to perform, and other factors, an increasing number of memory chips fail to meet the increasingly stringent design specifications.
An adjustable data delay circuit comprises a clocked data passing circuit that receives a clock signal and a data signal. An adjustable time delay circuit is coupled to the clock signal for adjusting the time the data is delivered to an output terminal relative to the clock signal. The adjustable time delay circuit includes a plurality of delay gates, each individually selected by control signals. One path in the time delay circuit that includes the desired delay gate is selected by the control signals. The clock signal passing through the selected delay gate is then used to control the time when the data is delivered to the output terminal.
In one embodiment, the control signals are made by selectively coupling a pattern of control inputs to a reference voltage.
In another embodiment, the passgates are arranged in a plurality of columns such that each column has a number of passgates that is an integer power of 2.